Estimation of step-by-step induced stress in a sequential process integration of nano-scale SOS MOSFETs with high-k gate dielectrics

被引:28
作者
Chatterjee, Sulagna [1 ]
Chowdhury, Basudev Nag [2 ]
Das, Anindita [2 ]
Chattopadhyay, Sanatan [1 ]
机构
[1] Univ Calcutta, Dept Elect Sci, Kolkata 700009, India
[2] Univ Calcutta, Ctr Res Nanosci & Nanotechnol, Kolkata 700098, India
关键词
STRAINED-SI; IMPACT; RELIABILITY; DIFFUSION; SILICON;
D O I
10.1088/0268-1242/28/12/125011
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The current work proposes a novel technique to incorporate process-induced uni-axial stress for significant mobility boosting in high-performance metal-oxide-semiconductor field-effect-transistors. It has been shown that two existing standard techniques, namely, silicon-on-sapphire and high-k gate dielectrics can be combined to develop such technology. Sapphire has very high elastic constant and thermal expansion coefficient, thereby capable of inducing a significant amount of stress which is observed to be biaxial in nature. However, with the incorporation of different materials during process integration, such biaxial stress is gradually changed to uni-axial nature. The high-k gate dielectric plays the key role in converting the biaxial stress to uni-axial. Several high-k gate dielectrics have been studied and titanium oxide (TiO2) is observed to maximize the induced stress and also effective to convert it to uni-axial. A final average longitudinal channel stress of 0.73 GPa has been obtained.
引用
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页数:7
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