Engineering Negative Differential Resistance in NCFETs for Analog Applications

被引:81
作者
Agarwal, Harshit [1 ]
Kushwaha, Pragya [1 ]
Duarte, Juan Pablo [1 ]
Lin, Yen-Kai [1 ]
Sachid, Angada B. [1 ]
Kao, Ming-Yen [1 ]
Chang, Huan-Lin [1 ]
Salahuddin, Sayeef [1 ]
Hu, Chenming [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
关键词
Analog applications; negative capacitance field-effect transistor (NCFET); negative differential resistance (NDR); sub-60; mv/decade; CAPACITANCE; MODEL; FINFETS;
D O I
10.1109/TED.2018.2817238
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In negative capacitancefield- effect transistors (NCFETs), drain current may decrease with increasing V-ds in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance (g (ds)) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce g(ds) degradation in short-channel devices. Small and positive gds is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V V-dd is used as the baseline device in this paper.
引用
收藏
页码:2033 / 2039
页数:7
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