Thermal sub-modeling of high density interconnect substrates

被引:5
|
作者
de Oca, TM [1 ]
Joiner, B [1 ]
Johnson, Z [1 ]
机构
[1] Motorola Inc, Semicond Prod Sector, Austin, TX 78721 USA
来源
ITHERM 2002: EIGHTH INTERSOCIETY CONFERENCE ON THERMAL AND THERMOMECHANICAL PHENOMENA IN ELECTRONIC SYSTEMS, PROCEEDINGS | 2002年
关键词
flip chip; ball grid array; thermal modeling; finite element simulation; electronic packaging; Theta; Theta-JA; thermal resistance; thermal characterization;
D O I
10.1109/ITHERM.2002.1012512
中图分类号
O414.1 [热力学];
学科分类号
摘要
High-performance integrated circuits require high-leadcount and low-inductance first-level packaging solutions. Suitable packaging options often involve the use of high-density interconnect (HDI, or "microvia") substrate technology. Typical HDI substrates begin with a polymer-glass fiber core laminate, upon which high-density microvia structures are built. The finished substrate can contain hundreds of plated thru-holes (PTHs), microvias, and a dense network of interconnect traces that span four or more layers. The specific arrangement, connection, and layout of these features will affect the effective thermal conductivity of the substrate. This paper extends a previously developed two-dimensional submodeling approach to three-dimensional via structures to allow simple geometric representation of the substrate while accurately determining the out-of-plane conductivity. The technique is applied to two flip-chip plastic ball grid array (FC-PBGA) packages with HDI substrates. The sub-model and package-level modeling results are validated using experimental measurements of die, substrate, and PWB temperature for both convection and conduction cooling environments. Good agreement between simulation and experiment are obtained.
引用
收藏
页码:618 / 625
页数:8
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