Predictive Control Using an FPGA With Application to Aircraft Control

被引:71
作者
Hartley, Edward Nicholas [1 ]
Jerez, Juan Luis [2 ]
Suardi, Andrea [2 ]
Maciejowski, Jan M. [1 ]
Kerrigan, Eric C. [2 ,3 ]
Constantinides, George A. [2 ]
机构
[1] Univ Cambridge, Dept Engn, Cambridge CB2 1PZ, England
[2] Univ London Imperial Coll Sci Technol & Med, Dept Elect & Elect Engn, London SW7 2AZ, England
[3] Univ London Imperial Coll Sci Technol & Med, Dept Aeronaut, London SW7 2AZ, England
基金
英国工程与自然科学研究理事会;
关键词
Aerospace control; field-programmable gate arrays (FPGAs); optimization methods; predictive control; INTERIOR-POINT METHODS; IMPLEMENTATION;
D O I
10.1109/TCST.2013.2271791
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Alternative and more efficient computational methods can extend the applicability of model predictive control (MPC) to systems with tight real-time requirements. This paper presents a system-on-a-chip MPC system, implemented on a field-programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) quadratic program (QP) solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-in-the-loop testbench controlling a nonlinear simulation of a large airliner. This paper considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a midrange FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC.
引用
收藏
页码:1006 / 1017
页数:12
相关论文
共 40 条
[1]  
Alessio A, 2009, LECT NOTES CONTR INF, V384, P345, DOI 10.1007/978-3-642-01094-1_29
[2]  
[Anonymous], 2012, GARTEUR RECOVER BENC
[3]  
[Anonymous], MICROBLAZE PROC REF
[4]  
[Anonymous], 2012, HDL COD US GUID R201
[5]  
[Anonymous], 2008, FPGA P IFAC P VOLUME
[6]  
[Anonymous], 2012, P APP EUR CONTR C
[7]  
Basterretxea K., 2011, Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), P327, DOI 10.1109/AHS.2011.5963955
[8]   The explicit linear quadratic regulator for constrained systems [J].
Bemporad, A ;
Morari, M ;
Dua, V ;
Pistikopoulos, EN .
AUTOMATICA, 2002, 38 (01) :3-20
[9]  
Betts JT, 2010, ADV DES CONTROL, P1, DOI 10.1137/1.9780898718577
[10]   A co-processor FPGA platform for the implementation of real-time model predictive control [J].
Bleris, Leonidas G. ;
Vouzis, Panagiotis D. ;
Arnold, Mark G. ;
Kothare, Mayuresh V. .
2006 AMERICAN CONTROL CONFERENCE, VOLS 1-12, 2006, 1-12 :1912-+