A reconfigurable approach to implement neural networks for engineering application

For different engineering applications, neural networks vary in scale, topology, transfer functions and learning algorithms. A reconfigurable approach for neural hardware implementation is proposed: neural algorithms are decomposed into several basic computations executed by reconfigurable processing units (RPU), which are designed carefully as IP (Intellectual Properties) cores and saved in core library; all the RPUs are interconnected in regular systolic arrays; when neural networks changed, new hardware can be reconfigured using FPGA and IP cores. Some key issues in implementation are discussed and a platform is developed for this approach. Comparisons with other implementations show that this approach has higher performances also with the flexible features.