Self-synchronization of an array of programmable oscillators (Clocks)

We present the CMOS circuit design and realization of an architecture for synchronizing multiple programmable oscillators (nodes). This circuit performs phase locking and locks to a common frequency with constant phase differences The nodes are Digitally-Controlled-Oscillators (DCOs) coupled via vector multipliers implemented by composing (analog) CMOS Gilbert Multipliers. The overall 3-node example circuit presented here includes on-chip inductors, and occupies total of 712.65 mu by 568.2 mu area in the 0.5 mu m technology process. This design is scalable to large numbers of nodes as well as finer feature size technologies.