A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells

This paper presents a fully synthesized 0.4-V analog biquad filter in a 0.13-mu m CMOS technology using digital standard cells. In contrast to a custom-designed inverter-based amplifier in the conventional design, a new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper. Furthermore, by employing feedforward compensation for loop stability, a new fully synthesized, reprogrammable, multistage operational amplifier (OPAMP) array based on the uOP is introduced which provides variable gain and bandwidth depending on the desired performance. As a proof of concept, a second-order switched-R-MOSFET-C analog filter is implemented. All the active blocks in the analog filter, such as the OPAMPs and matched-RC duty-cycle generator, are implemented using digital gates. The filter is realized using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17-dB-peak spurious free dynamic range and a tunable bandwidth of 1.7-2.5 MHz while consuming only 0.8 mW of power from a 0.4-V analog supply and a 1-V supply for the switches.