A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

被引：37

作者：

Li, Xueqing ^{[1
]}

Wei, Qi ^{[1
]}

Xu, Zhen ^{[1
]}

Liu, Jianan ^{[1
]}

Wang, Hui ^{[1
]}

Yang, Huazhong ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2014年 / 61卷 / 08期

基金：

美国国家科学基金会;

关键词：

Digital-to-analog converter (DAC); interleaving; return-to-zero (RZ); spurious-free dynamic range (SFDR); GRADIENT ERROR COMPENSATION; SFDR; CONVERTER; SEQUENCE; DBC;

D O I：

10.1109/TCSI.2014.2332248

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 mu m CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85 x 0.65 mm(2).

引用

页码：2337 / 2347

页数：11

共 40 条

[31]

Tang Y., 2013, Dynamic Mismatch Mapping for Digitally-Assisted DACs

[32] A 14 bit 200 MS/s DAC With SFDR >78 dBc, IM3 <-83 dBc and NSD <-163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping [J].

Tang, Yongjian ;

Briaire, Joost ;

Doris, Kostas ;

van Veldhoven, Robert ;

van Beek, Pieter C. W. ;

Hegt, Hans Johannes A. ;

van Roermund, Arthur H. M. .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (06) :1371-1381

[33] A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz [J].

Tseng, Wei-Hsin ;

Fan, Chi-Wei ;

Wu, Jieh-Tsorng .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (12) :2845-2856

[34] A 7.2 GSa/s, 14 Bit or 12 GSa/s, 12 Bit Signal Generator on a Chip in a 165 GHz fT BiCMOS Process [J].

Van de Sande, Frank ;

Lugil, Nico ;

Demarsin, Filip ;

Hendrix, Zeger ;

Andries, Alvin ;

Brandt, Peter ;

Anklam, William ;

Patterson, Jeffery S. ;

Miller, Brian ;

Rytting, Michael ;

Whaley, Mike ;

Jewett, Bob ;

Liu, Jacky ;

Wegman, Jake ;

Poulton, Ken .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2012, 47 (04) :1003-1012

[35]

van den Bosch A., 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), P1193, DOI 10.1109/ICECS.1999.814383

[36] A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter [J].

Van den Bosch, A ;

Borremans, MAF ;

Steyaert, MSJ ;

Sansen, W .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :315-324

[37]

Van den Bosch A, 2000, ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV, P105, DOI 10.1109/ISCAS.2000.858699

[38] A 14-bit intrinsic accuracy Q2 Random Walk CMOS DAC [J].

Van der Plas, GAM ;

Vandenbussche, J ;

Sansen, W ;

Steyaert, MSJ ;

Gielen, GGE .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (12) :1708-1718

[39] Output impedance analysis of digital-to-analogue converters [J].

Wu, X. ;

Steyaert, M. .

ELECTRONICS LETTERS, 2011, 47 (24) :1314-U25

[40]

Xueqing Li, 2011, 2011 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), P216, DOI 10.1109/ICECS.2011.6122252

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