A 14 Bit 500 MS/s CMOS DAC Using Complementary Switched Current Sources and Time-Relaxed Interleaving DRRZ

被引：37

作者：

Li, Xueqing ^{[1
]}

Wei, Qi ^{[1
]}

Xu, Zhen ^{[1
]}

Liu, Jianan ^{[1
]}

Wang, Hui ^{[1
]}

Yang, Huazhong ^{[1
]}

机构：

[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2014年 / 61卷 / 08期

基金：

美国国家科学基金会;

关键词：

Digital-to-analog converter (DAC); interleaving; return-to-zero (RZ); spurious-free dynamic range (SFDR); GRADIENT ERROR COMPENSATION; SFDR; CONVERTER; SEQUENCE; DBC;

D O I：

10.1109/TCSI.2014.2332248

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 mu m CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85 x 0.65 mm(2).

引用

页码：2337 / 2347

页数：11

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