Mixed-criticality scheduling upon varying-speed processors

被引:20
作者
Baruah, Sanjoy [1 ]
Guo, Zhishan [1 ]
机构
[1] Univ N Carolina, Chapel Hill, NC 27599 USA
来源
IEEE 34TH REAL-TIME SYSTEMS SYMPOSIUM (RTSS 2013) | 2013年
基金
美国国家科学基金会;
关键词
ALGORITHM;
D O I
10.1109/RTSS.2013.15
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A varying-speed processor is characterized by two execution speeds: a normal speed and a degraded speed. Under normal circumstances it will execute at its normal speed; conditions during run-time may cause it to execute more slowly (but no slower than at its degraded speed). The problem of executing an integrated workload, consisting of some more important components and some less important ones, upon such a varying-speed processor is considered. It is desired that all components execute correctly under normal circumstances, whereas the more important components should execute correctly (although the less important components need not) if the processor runs at any speed no slower than its specified degraded speed.
引用
收藏
页码:68 / 77
页数:10
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