SMV Methodology enhancements for High Speed I/O links of SoCs

被引：0

作者：

Viveros-Wacher, Andres ^{[1
]}

Alejos, Ricardo ^{[1
]}

Alvarez, Liliana ^{[1
]}

Diaz-Castro, Israel ^{[1
]}

Marcial, Brenda ^{[1
]}

Motola-Acuna, Gaston ^{[1
]}

Vega-Ochoa, Edgar-Andrei ^{[1
]}

机构：

[1] Intel Corp, Intel Guadalajara Design Ctr, Tlaquepaque 45600, Mexico

来源：

2014 IEEE 32ND VLSI TEST SYMPOSIUM (VTS) | 2014年

关键词：

System-on-Chip; Post-Silicon Electrical Validation; System Marginality Validation; High Speed I/O; Unit per Million;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an enhanced methodology to validate High Speed I/O links. The methodology outlines a stress method selection process, statistical techniques to optimize volume data collection as well as a method to determine when to perform UPM calculations.

引用

页数：5

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