Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis

被引：106
作者：
Saurabh, Sneh [1 ]
Kumar, M. Jagadesh [1 ]
机构：
[1] Indian Inst Technol, Dept Elect Engn, New Delhi 110016, India
来源：
JAPANESE JOURNAL OF APPLIED PHYSICS | 2009年 / 48卷 / 06期
关键词：
ON-INSULATOR; SOI CMOS; FET; SILICON; DEVICE; SIMULATION; MOSFETS; MODEL;
D O I：
10.1143/JJAP.48.064503
中图分类号：
O59 [应用物理学];
学科分类号：
摘要：
Tunnel field effect transistor (TFET) devices are attractive as they show good scalability and have very low leakage current. However they suffer from low on-current and high threshold voltage. In order to employ the TFET for circuit applications, these problems need to be tackled. In this paper, a novel lateral strained double-gate TFET (SDGTFET) is presented. Using device simulation, we show that the SDGTFET has a higher on-current, low leakage, low threshold voltage, excellent subthreshold slope, and good short channel effects and also meets important ITRS guidelines. (C) 2009 The Japan Society of Applied Physics
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页数：7
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