An optimized embedded adder for digital signal processing applications

In this paper, an embedded logic full adder (PRO-FA) circuit in transistor level is proposed that reduces logic complexity, consumes low power, and is low area. The design is implemented for 1 bit and then is further extended to 64 bits. The area obtained for 1-bit PRO-FA is 2.85 mu m(2) and is built using only 13 transistors. The PDP of the proposed adder is 459.4x 10(-18) Ws and ADP is 128.25 mu m(2) ps and is compared with the earlier reported designs. Furthermore, a 16-, 32-, 64-bit both linear and square-root carry select adder/subtractor (CSLAS) structure is proposed. Realistic testing in terms of power and delay is performed for the proposed logic by implementing it on 8 x 8 modified Booth, array, and Wallace tree multiplier architectures. The efficiency of the proposed circuits in DSP architecture like 4-tap FIR filter is demonstrated. Overall delay for CSLAS is reduced to 70% when compared to the conventional one. The implementations are done using the Cadence Virtuoso tool with TSMC 28 nm LP CMOS technology and are found to have power savings of up to 76%. The present proposed architectures offer significant improvement in terms of power and speed in comparison to other reported architectures.