Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process

被引：4

作者：

De Munck, K. ^{[1
]}

Bogaerts, J. ^{[2
]}

Tezcan, D. S. ^{[2
]}

De Moor, P. ^{[2
]}

Sedky, S. ^{[3
]}

Van Hoof, C. ^{[2
]}

机构：

[1] Katholieke Univ Leuven, B-3001 Louvain, Belgium

[2] IMEC, B-3001 Louvain, Belgium

[3] Amer Univ Cairo, Yousef Jameel Sci & Technol Res Ctr, Cairo, Egypt

来源：

ELECTRONICS LETTERS | 2009年

关键词：

CMOS integrated circuits;

D O I：

10.1049/el:20082812

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Thinned backside illuminated CMOS imagers were developed, having a thick epitaxial layer with a graded doping concentration. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. Following appropriate backside treatment, high quantum efficiency above 80% between 400 and 870 nm was obtained, in agreement with simulation.

引用

页码：49 / 51

页数：3

共 7 条

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