Design of Efficient AES Architecture for Secure ECG Signal Transmission for Low-power IoT Applications

被引:6
|
作者
Janveja, Meenali [1 ]
Paul, Bikram [1 ]
Trivedi, Gaurav [1 ]
Vijayakanthi, Gonella [2 ]
Agrawal, Astha [2 ]
Jan, Pidanic [3 ]
Nemec, Zdenek [3 ]
机构
[1] Indian Inst Technol Guwahati, Dept Elect & Elect Engn, Gauhati, India
[2] NIT Rourkela, Dept Elect & Instrumentat Engn, Rourkela, Odisha, India
[3] Univ Pardubice, Dept Elect Engn, Pardubice, Czech Republic
来源
PROCEEDINGS OF THE 2020 30TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA) | 2020年
关键词
Cryptography; AES; FPGA; ECG signal; Folding; Xilinx; ZedBoard; HIGH-THROUGHPUT; PERFORMANCE EVALUATION; FPGA IMPLEMENTATION; ALGORITHM;
D O I
10.1109/radioelektronika49387.2020.9092417
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Cryptography has an important role in securing information which has gained prominence due to the digitization. Exchange of sensitive personal data such as medical information tends to take place frequently throughout the globe; therefore, protecting data from unauthorized adversary access is imperative. Advanced encryption standard (AES) algorithm is one of the algorithms which is broadly employed because of its exemplary security and usage in extensive applications. This research proposes a modified folded pipelined architecture of an AES algorithm for resources constraint applications. The folding transformation controls the circuit functionalities by time-multiplexing operations to a single functional unit and reduces its area considerably. The proposed architecture is implemented using fewer resources, hence, improves area and the power requirements as compared to the conventional algorithm. The work presented in this paper is applicable for encrypting and decrypting personalized Electrocardiograph (ECG) signals for secure transmission. The architecture proposed in this paper reduces the area requirements by 83% and power by 96.8% enabling its hardware implementation more efficient than the conventional AES. Due to its low power and area requirements, the architecture presented in this paper can be used for portable Internet of things (IoT) applications as well.
引用
收藏
页码:29 / 34
页数:6
相关论文
共 42 条
  • [31] A Speed- and Power-Efficient SPIHT Design for Wearable Quality-On-Demand ECG Applications
    Hsieh, Jui-Hung
    Hung, King-Chu
    Lin, Yu-Ling
    Shih, Meng-Ju
    IEEE JOURNAL OF BIOMEDICAL AND HEALTH INFORMATICS, 2018, 22 (05) : 1456 - 1465
  • [32] Modular Evaluation System for Low-Power Applications Educating undergraduate students in advanced digital design
    Schwandt, Andrea
    Winzker, Marco
    2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 364 - 367
  • [33] Machine learning on-a-chip: A high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications
    Sun, Yuwen
    Cheng, Allen C.
    COMPUTERS IN BIOLOGY AND MEDICINE, 2012, 42 (07) : 751 - 757
  • [34] A Low-Power and Bandwidth-Efficient Motion Estimation IP Core Design Using Binary Search
    Wang, Shih-Hao
    Tai, Shih-Hsin
    Chiang, Tihao
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 2009, 19 (05) : 760 - 765
  • [35] An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications
    Ganjikunta, Ganesh Kumar
    Sahoo, Subhendu Kumar
    INTEGRATION-THE VLSI JOURNAL, 2017, 57 : 125 - 131
  • [36] Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications
    Pons Jean-François
    Brault Jean-Jules
    Savaria Yvon
    Analog Integrated Circuits and Signal Processing, 2013, 77 : 169 - 182
  • [37] Modeling, design and implementation of a low-power FPGA based asynchronous wake-up receiver for wireless applications
    Jean-Francois, Pons
    Jean-Jules, Brault
    Yvon, Savaria
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2013, 77 (02) : 169 - 182
  • [38] VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design
    Van, Lan-Da
    Lin, Chin-Teng
    Yu, Yuan-Chu
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2007, E90A (08) : 1644 - 1652
  • [39] VLSI-Design and FPGA-Implementation of GMSK-Demodulator Architecture Using CORDIC Engine for Low-Power Application
    Kumar, Lalit
    Mittal, Deepak Kumar
    Shrestha, Rahul
    2016 IEEE ANNUAL INDIA CONFERENCE (INDICON), 2016,
  • [40] Run-time reconfigurable multi-precision floating point multiplier design for high speed, low-power applications
    Arish, S.
    Sharma, R. K.
    2ND INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) 2015, 2015, : 902 - 907