A system level optimization of on-chip thermoelectric cooling via Taguchi-Grey method

In this paper, a framework for the system level optimization of the thin-film thermoelectric cooler (TFTEC) in 3D electronic packaging is developed based on Taguchi-Grey method. The influences of the size effect, the geometric effect, the parasitic effect and the localized hotspot are comprehensively considered. An L-25 (5(6)) orthogonal array is employed to assess the influences of the leg height, the fill-ratio, the electrode height, the gap distance, the hotspot size and the hotspot heat flux on the passive and active cooling effects of the TFTEC. The results show that the electrode height, acting as the primary factor, contributes 45.5% and 45.3% on the passive cooling and active cooling, respectively. The contribution ratios of hotspot size and hotspot heat flux to passive cooling reach 21.4% and 14.7%, respectively. The contribution ratios of leg height and gap distance to active cooling reach 25.7% and 18.8%, respectively. The optimum design factors for maximizing the cooling effects are also approached by the Grey relational analysis. A passive cooling of 16.82 ? and a maximum active cooling of 12.29 ? are achieved, leading to a total localized cooling of 29.11 ? for a chip hotspot.