NA/sigma optimisation strategies for an advanced DUV stepper applied to 0.25 mu m and sub-0.25 mu m critical levels

In this paper, the results of an NA-sigma optimisation study are reported, carried out experimentally for an advanced ASML PAS5500/300 deep-UV stepper. The work has been primarily focused on a 0.25 and sub-0.25 mu m gate layer in a logic CMOS process. A positive and negative tone resist process have been compared in terms of CD control and line-end shortening. Dry etch effects and across-field behaviour has been taken into account. Furthermore the contact level of the 0.25 mu m process have been optimised. Effects of layer dependent NA-sigma settings on overlay have been studied.