Enabling Scalable Disintegrated Computing Systems With AWGR-Based 2.5D Interconnection Networks

被引:6
作者
Fotouhi, Pouya [1 ]
Werner, Sebastian [1 ]
Proietti, Roberto [1 ]
Xiao, Xian [1 ]
Yoo, S. J. Ben [1 ]
机构
[1] Univ Calif Davis, Dept Elect & Comp Engn, Davis, CA 95616 USA
关键词
2.5D integration; Interconnection networks; Silicon photonics; SILICON-PHOTONIC NETWORK; OPTICAL NOC TOPOLOGIES; ON-CHIP; POWER-EFFICIENT; LASER;
D O I
10.1364/JOCN.11.000333
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
2.5D integrated systems exploiting electronic interposers to tightly integrate multiple processor dies into the same package suffer from significant performance degradation caused by the large latency overheads of their die-to-die multihop electrical interconnection networks. Silicon-photonic interposers with wavelength-routed interconnects can overcome this issue by enabling directly connected, scalable topologies while exhibiting low-energy optical communication even at large distances. This paper studies the use of an arrayed waveguide grating router (AWGR) as a scalable, low-latency silicon-photonic interconnection fabric for computing systems with up to 256 cores. Our results indicate that AWGRs could be a key enabler for large-scale interposer systems, offering an average performance speed-up of at least 1.25x with 1.32x lower power for 256 cores compared to state-of-the-art electrical networks, while offering a more compact solution compared to alternative photonic interconnects.
引用
收藏
页码:333 / 346
页数:14
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