Performance Analysis of Cascaded Multilevel Inverter with Reduced Switched Topology

被引：0
|
作者：
Garapati, Durga Prasad [1 ]
Jegathesan, V [2 ]
Nalli, Praveen Kumar [1 ]
Bhukya, Ramu [1 ]
Bharathi, Bommina Sravani Vijaya [1 ]
Duvvuri, S. S. S. R. Sarathbabu [1 ]
机构：
[1] Shri Vishnu Engn Coll Women Autonomous Bhimavaram, Dept EEE, Bhimavaram, India
[2] Karunya Inst Technol & Sci, Dept EEE, Coimbatore, Tamil Nadu, India
来源：
2018 IEEE 8TH POWER INDIA INTERNATIONAL CONFERENCE (PIICON) | 2018年
关键词：
Multilevel Inverter; Photovoltaic; Reduced Switch; Total Harmonic Distortion; CONVERTERS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Multilevel inverter plays a crucial role in industrial applications. The performance of cascaded multilevel inverter (CMLI) with reduced switch count is analyzed in this paper. If the switches have been increased the switching loss and THD will increase. The preferred topology is simulated for seven level and fifteen level by considering isolated DC source and PV. The reduced % THD is identified compare to other topologies. Four switches continuously working at fundamental switching frequency is considered as one of the advantage of the topology.
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页数：5
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