Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-VDDmin, and slow read access time (T-AC) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (IDC-SET) resulting from the wide distribution of write (SET)-times (T-SET). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately 1.8 + x greater sensing margin for lower and a 1.7 + x faster read speed across a wide range, compared with conventional VSAs. A 4T self-boost-write-termination (SBWT) scheme is proposed to cut off the IDC-SET of devices with a rapid T-SET. The SBWT scheme reduces 99 + % of the IDC-SET with an area penalty below 0.5%. A fabricated 512 row 28 nm 1 Mb ReRAM macro achieved T-AC = 404 ns when VDD = 0.27 V and confirmed the IDC-SET cutoff by the SBWT.