A Pseudo Cross-Coupled Switch-Capacitor Based DC-DC Boost Converter for High Efficiency and High Power Density

被引:14
作者
Das, Tamal [1 ]
Prasad, Sankalan [2 ]
Dam, Samiran [3 ]
Mandal, Pradip [3 ]
机构
[1] Cadence Design Syst Inc, Bangalore, Karnataka, India
[2] Intel India Technol Pvt Ltd, Bangalore, Karnataka, India
[3] IIT, E&ECE Dept, Kharagpur, W Bengal, India
关键词
Dynamic frequency tuning; dynamic leaker; power density; shoot-through current; switched; capacitor (SC) dc-dc converters; CHARGE PUMP; DOUBLER;
D O I
10.1109/TPEL.2014.2297972
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we propose a fully-integrated switch-capacitor (SC) dc-dc boost converter having high power efficiency, low output ripple, and high power density. It uses a switching scheme called nonoverlapped rotational time-interleaving (NORI) which eliminates shoot-through loss as well mitigates the adverse effect of dead times between successive charging and discharging phases which results into a small ripple. A basic cross-coupled voltage doubler has been adopted to implement the NORI scheme working over a wide range of switching frequencies. Dynamic adjustment of the frequency provides high power density as well as maintains high power efficiency over a wide load current range. The proposed converter has been fabricated in 0.18-mu m CMOS thick gate process for 3.3 to 5.5 V conversion and output ripple not more than 0.5% of the output voltage. The converter uses only 440 pF to deliver up to 25 mA at 5.3 V regulated output. The measured peak power efficiency is 89% at 20 mA for unregulated output. With mixed mode regulations, the measured efficiency of the converter including analog blocks is 83.5% at 15 mA, while the overall efficiency is 75%. Power density of the designed converter is more than 0.85 W/mm(2) considering the capacitor area.
引用
收藏
页码:5961 / 5974
页数:14
相关论文
共 23 条
[1]  
Cabrini A., 2006, ELECT LETT
[2]   ON-CHIP HIGH-VOLTAGE GENERATION IN MNOS INTEGRATED-CIRCUITS USING AN IMPROVED VOLTAGE MULTIPLIER TECHNIQUE [J].
DICKSON, JF .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (03) :374-378
[3]  
Evzelman M, 2012, IEEE ENER CONV, P1592, DOI 10.1109/ECCE.2012.6342623
[4]   A high-efficiency CMOS voltage doubler [J].
Favrat, P ;
Deval, P ;
Declercq, MJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (03) :410-416
[5]   A compact switched-capacitor regulated charge pump power supply [J].
Gregoire, B. Robert .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (08) :1944-1953
[6]   Practical Performance Analysis of Complex Switched-Capacitor Converters [J].
Henry, Jordan M. ;
Kimball, Jonathan W. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2011, 26 (01) :127-136
[7]   CMOS Charge Pump With Transfer Blocking Technique for No Reversion Loss and Relaxed Clock Timing Restriction [J].
Kim, Joung-Yeal ;
Jun, Young-Hyun ;
Kong, Bai-Sun .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2009, 56 (01) :11-15
[8]  
Kumar PVR, 2009, I SYMPOS LOW POWER E, P81
[9]   Switching noise and shoot-through current reduction techniques for switched-capacitor voltage doubler [J].
Lee, H ;
Mok, PKT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (05) :1136-1146
[10]   Robust multiple-phase switched-capacitor DC-DC power converter with digital interleaving regulation scheme [J].
Ma, Dongsheng ;
Luo, Feng .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2008, 16 (06) :611-619