Post-Processing Refinement for Semi-Global Matching Algorithm Based on Real-Time FPGA

The Semi-Global Matching (SGM) algorithms and their hardware accelerators, which emphasize stereo matching rather than occlusion filling, have been developed in the last few years. However, filling occlusions is indispensable for many real-world applications. This work presents a pixel-level pipeline architecture for the post-processing of SGM, which refines disparity through a left-right check, and multi-directional occlusion filling refinement. The hardware architecture based on optimization algorithms is on the Stratix-IV platform, and it consumes about 5720 LUTs, 12961 registers, and 2.15M bits of on-chip memory. The maximum working frequency can reach up to 95.15 MHz for the 640x480 resolution video and 128 disparity range with the power dissipation of 1.46 W and 320 frames per second processing speed.