"Smart" TDDB algorithm for investigating degradation in high-κ gate dielectric stacks under constant voltage stress

被引：4

作者：

Young, Chadwin D. ^{[1
]}

Bersuker, Gennadi ^{[1
]}

Tun, Joey ^{[2
]}

Choi, Rino ^{[3
]}

Heh, Dawei ^{[1
]}

Lee, Byoung Hun ^{[1
]}

机构：

[1] SEMATECH, Austin, TX 78640 USA

[2] Keithley Instruments, Cleveland, OH 44139 USA

[3] Inha Univ, Inchon 402751, South Korea

来源：

MICROELECTRONIC ENGINEERING | 2009年 / 86卷 / 03期

关键词：

High-kappa; Breakdown; Stress-induced leakage current; Constant voltage stress; Time dependent dielectric breakdown; TRAP GENERATION;

D O I：

10.1016/j.mee.2008.09.024

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new "smart" algorithm with adaptive testing is developed for automatically monitoring gate dielectric degradation during CVS using SILC. In this approach, stress current is monitored with a sampling rate as fast as similar to 2 ms/point while SILC data are collected based on stress current changes and/or time intervals. This automated test was applied to study degradation of nMOS transistors with TiN/HfO(2) gate stacks where changes in the SILC data correlate directly with transitions in the stress current. From this SILC data, the differential resistance can be extracted and used to monitor conductivity throughout the degradation phase until breakdown. (C) 2008 Elsevier B.V. All rights reserved.

引用

页码：287 / 290

页数：4