A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

被引：32
作者：
Farjad-Rad, R [1 ]
Nguyen, A
Tran, JM
Greer, T
Poulton, J
Dally, WJ
Edmondson, JH
Senthinathan, R
Rathi, R
Lee, MJE
Ng, HT
机构：
[1] Rambus Inc, Los Altos, CA 94022 USA
[2] Velio Commun Inc, Milpitas, CA 95035 USA
[3] Stanford Univ, Stanford, CA 94305 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 09期
关键词：
clock and data recovery (CDR); clock multiplication; frequency tracking/acquisition; high-speed transceivers; injection locking; jitter filtering; multiplying DLL; phase interpolation;
D O I：
10.1109/JSSC.2004.831457
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 0.622-8-Gb/s clock and data recovery (CDR) circuit using injection locking for jitter suppression and phase interpolation in high-bandwidth system-on-chip solutions is described. A slave injection locked oscillator (SILO) is locked to a tracking aperture-multiplying DLL (TA-MDLL) via a coarse phase selection multiplexer (MUX). For the fine timing vernier, an interpolator DAC controls the injection strength of the MUX output into the SILO. This 1.2-V 0.13-mum CMOS CDR consumes 33 mW at 8 Gb/s. Die area including voltage regulator is 0.08 mm(2). Recovered clock jitter is 49 ps pk-pk at a 200-ppm bit-rate offset.
引用
收藏
页码：1553 / 1561
页数：9
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