A low-power inverted ladder D/A converter

被引:8
作者
Perelman, Yevgeny [1 ]
Ginosar, Ran [1 ]
机构
[1] Technion Israel Inst Technol, Dept Elect Engn, VLSI Syst Res Ctr, IL-32000 Haifa, Israel
关键词
digital-to-analog converter (DAC); low power; resistor ladder;
D O I
10.1109/TCSII.2006.875313
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Interpolating, dual resistor ladder digital-to-analog converters (DACs) typically use the fine, least significant bit (LSB) ladder floating upon the static most significant bit (MSB) ladder. The usage of the LSB ladder incurs a penalty in dynamic performance due to the added output resistance and switch matrix parasitic capacitance. Current biasing of the LSB ladder addresses this issue by employing active circuitry. We propose an inverted ladder DAC, where an MSB ladder slides upon two static LSB ladders. While using no active components this scheme achieves lower output resistance and parasitic capacitance for a given power budget. We present a 0.35-mu m, 3.3-V implementation consuming 22-mu A current with output resistance of 40 k Omega and effective parasitic capacitance of 650 fF.
引用
收藏
页码:497 / 501
页数:5
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