VERIFICATION OF SOFT-ERROR RATE ESTIMATION METHOD IN A LOGIC LSI

被引：0
|
作者：
Makino, T. [1 ]
Onoda, S. [1 ]
Hirao, T. [1 ]
Ohshima, T. [1 ]
Kobayashi, D. [2 ]
Hirose, K. [2 ]
机构：
[1] JAEA, Takasaki, Gunma 3701292, Japan
[2] Japan Aerosp Explorat Agcy JAXA, Sagamihara, Kanagawa 2298510, Japan
来源：
REPORT OF RESEARCH CENTER OF ION BEAM TECHNOLOGY, HOSEI UNIVERSITY, SUPPL NO 28 | 2010年 / 28卷
关键词：
SET PULSE WIDTHS; SOI;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
SET-induced soft-error rates (SERSET) in logic LSIs are estimated from SET pulse-widths measured in logic cells used in logic LSIs. The estimated rates are consistent with directly measured SERSETS for logic LSIs.
引用
收藏
页码：35 / 40
页数：6
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