Hydrogenated Poly-Si TFTS with a structure of source overlap and drain offset

Polycrystalline-silicon thin-film transistors (Poly-Si TFTs) with different source overlap lengths have been studied as a function of electrical stress time. Since the decrease of the on-current is found to be the dominant factor of the electrical degradation, the channel series resistance effect is more important than the leakage effect between the gate and the source region or in the channel. Before and after negative-bias stress of weak (4.8 MV/cm) and strong (7.2 MV/cm) electric fields to gate electrode at room temperature, the structure of 0.2-mu m source overlap shows optimal device characteristics in on/off current ratio, threshold voltage shift, and subthreshold swing.