Place and Route Considerations for Voltage Interpolated Designs

被引：1

作者：

Brownell, Kevin ^{[1
]}

Khan, Ali Durlov ^{[1
]}

Brooks, David ^{[1
]}

Wei, Gu-Yeon ^{[1
]}

机构：

[1] Harvard Univ, Sch Engn & Appl Sci, Cambridge, MA 02138 USA

来源：

ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2 | 2009年

关键词：

D O I：

10.1109/ISQED.2009.4810361

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Voltage interpolation is a promising post fabrication technique for combating the effects of process variations. The benefits of voltage interpolation are well understood. Its implementation in a VLSI-CAD flow has been considered through the synthesis stage. In this paper we study the implications of place and route on voltage interpolation. We evaluate multiple placement strategies, and conclude that a hybridization of forced placement and cluster boxing techniques results in minimum overhead.

引用

页码：594 / 600

页数：7

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