An FPGA-based Space-time Coded Telemetry Receiver

被引：3

作者：

Lavin, Christopher ^{[1
]}

Nelson, Brent ^{[1
]}

Palmer, Joseph ^{[1
]}

Rice, Michael ^{[1
]}

机构：

[1] Brigham Young Univ, Dept Elect & Comp Engn, Provo, UT 84604 USA

来源：

NAECON 2008 - IEEE NATIONAL AEROSPACE AND ELECTRONICS CONFERENCE | 2008年

关键词：

D O I：

10.1109/NAECON.2008.4806555

中图分类号：

V [航空、航天];

学科分类号：

08 ; 0825 ;

摘要：

The significant problem of data dropouts in aeronautical telemetry due to multiple transmit antennas has escalated as transmit data rates have increased. A proposed solution of using a space-time coded signal can resolve these data dropouts at the expense of increased receiver complexity. This paper describes an implementation overview of an FPGA-based space-time coded telemetry receiver and the various challenges associated with its realization. In addition, we discuss the productivity of the high-level design tool used in constructing the receiver, Xilinx System Generator for DSP. With some overhead in terms of FPGA fabric usage and clock speed, our estimates show a 2 - 3x productivity improvement over standard HDLs.

引用

页码：250 / 256

页数：7

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