A Physical Unclonable Function Chip Exploiting Load Transistors' Variation in SRAM Bitcells

被引：0

作者：

Okumura, S. ^{[1
]}

Yoshimoto, S. ^{[1
]}

Kawaguchi, H. ^{[1
]}

Yoshimoto, M. ^{[1
,2
]}

机构：

[1] Kobe Univ, Grad Sch Syst Informat, Kobe, Hyogo, Japan

[2] JST CREST, Kawaguchi, Saitama, Japan

来源：

2013 18TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) | 2013年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We propose a chip identification (ID) generating scheme with random variation of transistor characteristics in SRAM bitcells. In the proposed scheme, a unique fingerprint is generated by grounding both bitlines. It has high speed, and it can be implemented in a very small area overhead. We fabricated test chips in a 65-nm process and obtained 12,288 sets of unique 128-bit fingerprints, which are evaluated in this paper. The failure rate of the IDs is found to be 2.1 x 10(-12).

引用

页码：79 / 80

页数：2

共 44 条

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