An assessment of the location of As-grown electron traps in HfO2/HfSiO stacks

被引：37

作者：

Zhang, J. F. ^{[1
]}

Zhao, C. Z.

Zahid, M. B.

Groeseneken, G.

Degraeve, R.

De Gendt, S.

机构：

[1] Liverpool John Moores Univ, Sch Engn, Liverpool L3 3AF, Merseyside, England

[2] IMEC, Interuniv Microelect Ctr, B-3001 Heverlee, Belgium

[3] Katholieke Univ Leuven, B-3001 Heverlee, Belgium

来源：

IEEE ELECTRON DEVICE LETTERS | 2006年 / 27卷 / 10期

基金：

英国工程与自然科学研究理事会;

关键词：

defects; gate dielectrics; high-k; instability; oxides; reliability; traps;

D O I：

10.1109/LED.2006.882566

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Replacing SiON by high-kappa layers is a pressing issue for CMOS technologies. The presence of as-grown electron traps in HfO2 is a major obstacle, since they can induce threshold-voltage instability, reduce electron mobility, and result in early breakdown. Their location has not been clarified and is addressed in this letter. By selecting test conditions carefully and using samples with a progressive reduction of HfO2 thickness, the authors are able to rule out that traps are piled up near the HfO2/HfSiO interface. A uniform distribution throughout HfO2 does not agree with the test data, either. Results support that trapping is negligible near to one or both ends of the HfO2 layer when compared with trapping in the central region.

引用

页码：817 / 820

页数：4

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