A Sub-1 V Transient-Enhanced Output-Capacitorless LDO Regulator With Push-Pull Composite Power Transistor

被引：47

作者：

Chong, Sau Siong ^{[1
]}

Chan, Pak Kwong ^{[1
]}

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2014年 / 22卷 / 11期

关键词：

Composite power transistor; low-dropout (LDO) voltage regulator; low-voltage regulator; output-capacitorless (OCL) LDO regulator; push-pull; LOW-DROPOUT REGULATOR; LOW-QUIESCENT-CURRENT; VOLTAGE; FILTER; SOC;

D O I：

10.1109/TVLSI.2013.2290702

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

An output-capacitorless low-dropout (OCL-LDO) regulator with a push-pull composite power transistor is presented in this paper. Using the proposed composite transistor, the nondominant parasitic poles can be pushed to higher frequencies, leading to good stability. In addition, the slew rate limitation at the gate of the power transistor is improved greatly by the proposed push-pull structure. Implemented and fabricated in UMC 65-nm CMOS technology, the LDO regulator occupies only an active area of 0.0096 mm(2). The experimental results have shown that the regulator is able to operate at V-IN = 0.75 V and deliver a maximum load current of 50 mA with a dropout voltage of less than 250 mV. It consumes a quiescent current of 16.2 mu A and is able to settle within 1.2 mu s.

引用

页码：2297 / 2306

页数：10

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