Harmonic analysis and improvement of a new solid-state fault current limiter

被引:24
作者
Ahmed, MMR
Putrus, GA [1 ]
Ran, L
Xiao, LJ
机构
[1] Ind Educ Coll, Cairo, Egypt
[2] Northumbria Univ, Sch Engn & Technol, Newcastle Upon Tyne NE1 8ST, Tyne & Wear, England
[3] Univ Durham, Sch Engn, Durham DH1 3LE, England
[4] Univ Salford, Sch Engn, Manchester M45 7FN, Lancs, England
关键词
fault current limiters; harmonics; power quality and switched-mode power supply (SMPS);
D O I
10.1109/TIA.2004.830774
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This paper presents a harmonic study on a newly developed solid-state fault current limiter. Using this device, the supply voltage sag is reduced when a short-circuit fault occurs on a cable feeder in the downstream network, hence improving the power quality. The device will eventually isolate the faulted part from the healthy network. Harmonics caused by the fault current limiter are analyzed and a method is proposed to prevent undesirable harmonic interactions. Analytical and experimental results are compared with existing regulations. It is verified that, with precautions, the operation of the solid-state fault current limiter will not cause problems to either the supply network or the loads.
引用
收藏
页码:1012 / 1019
页数:8
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