Thermal-driven interconnect optimization by simultaneous gate and wire sizing

Temperature, as well as electromigration (EM), area, timing, and power, has become one of the most important concerns in nanometer circuit design. In this paper, we model the effects of thermal on both interconnect delay and EM reliability. Applying the least square estimator (LSE) method, we develop a posynomial formula to approximate interconnect temperature and present an algorithm to optimally solve the simultaneous interconnect temperature, EM, area, delay, and power optimization by sizing circuit components based on Lagrangian relaxation. Experimental results show that our algorithm is very effective, efficient, and economical.