Status and Trends in Ge CMOS Technology

被引：17

作者：

Claeys, C. ^{[1
]}

Mitard, J. ^{[1
]}

Hellings, G. ^{[1
]}

Eneman, G. ^{[1
]}

De Jaeger, B. ^{[1
]}

Witters, L. ^{[1
]}

Loo, R. ^{[1
]}

Delabie, A. ^{[1
]}

Sioncke, S. ^{[1
]}

Caymax, M. ^{[1
]}

Simoen, E. ^{[1
]}

机构：

[1] IMEC, B-3001 Leuven, Belgium

来源：

2013 INTERNATIONAL CONFERENCE ON SEMICONDUCTOR TECHNOLOGY FOR ULTRA LARGE SCALE INTEGRATED CIRCUITS AND THIN FILM TRANSISTORS (ULSIC VS. TFT 4) | 2013年 / 54卷 / 01期

关键词：

ATOMIC LAYER DEPOSITION; GERMANIUM MOSFETS; GATE; PERFORMANCE; OPPORTUNITIES; CHALLENGES; PMOSFET; FILMS; FIELD;

D O I：

10.1149/05401.0025ecst

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

Since the last decade there has been renewed interest in Ge-based technologies for deep submicron CMOS technologies. Whereas good performance data has been reported for p-channel MOSFETs this was not the case for the n-channel counterpart. This manuscript first reviews some key technological aspects for Ge processing, before outlining the status and trends for p-and n-channel Ge MOSFETs in relation to the ITRS specifications. Special attention will be given to GeSn technologies.

引用

页码：25 / 37

页数：13