A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach

被引：0

作者：

Tseng, HC ^{[1
]}

Ou, HH ^{[1
]}

Lin, CS ^{[1
]}

Liu, BD ^{[1
]}

机构：

[1] Natl Cheng Kung Univ, Dept Elect Engn, Tainan 70101, Taiwan

来源：

ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2004年

关键词：

flash analog-to-digital converter; rail-to-rail; low power; CMOS analog circuit; comparator;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a 6-bit 300-MSample/s(MS/s) flash analog-to-digital converter (ADC) with a novel complementary average-value (CAV) approach is proposed. Input signal is pre-processed and then steered to be compared with a fixed reference voltage level, which greatly simplifies the comparator design and thus power consumption is reduced. In addition, rail-to-rail input range can be achieved by the proposed CAV technique, and the offset as well as bubble errors can therefore be minimized as a result of similar operation condition arrangement of the comparators. Simulated with TSMC 1P5M 0.25 mum process parameters, the results show that INL < +/-0.4 LSB and DNL < +/-0.1 LSB, and SNDR of 32.7dB can be achieved. The converter consumes 35mW at 2.5 V power supply and the power efficiency of this converter is only 3.3pJ/conv-step which compares favorably with other published results.

引用

页码：252 / 256

页数：5

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