High-Performance Floating-Point VLSI Architecture of a Lifting-Based Wavelet Processor

被引：0

作者：

Guntoro, Andre ^{[1
]}

Momeni, Massoud ^{[1
]}

Keil, Hans-Peter ^{[1
]}

Glesner, Manfred ^{[1
]}

机构：

[1] Tech Univ Darmstadt, Inst Microelect Syst, Dept Elect Engn & Informat Technol, Darmstadt, Germany

来源：

ICSES 2008 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS, CONFERENCE PROCEEDINGS | 2008年

关键词：

Wavelets; Wavelet Transform; DSP; VLSI Architecture; Floating-Point;

D O I：

10.1109/ICSES.2008.4673350

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose a high-performance lifting-based wavelet processor that can perform various forward and inverse DWTs. Our architecture is based on NxM PEs which can perform either prediction or update on a continuous data stream in every clock cycle. In order to improve the accuracy, floating-point arithmetics are used to compute the transformation. To cope with different wavelet filters, we feature a multi-context configuration to select among various DWTs. For the 32-bit implementation, the estimated area of the proposed wavelet processor with 2x8 PEs in a 0.18-mu m technology is 4.8 mm square and the estimated operating frequency is 308 MHz.

引用

页码：35 / 38

页数：4

共 13 条

[1] A VLSI architecture for lifting-based forward and inverse wavelet transform [J].