An 8 1 Gb/s, 1.2V TIALA-Retimer in Standard 65nm CMOS

被引：0

作者：

Shahramian, Shahriar ^{[1
]}

Carusone, Anthony Chan ^{[1
]}

Schvan, Peter ^{[2
]}

Voinigescu, Sorin P. ^{[1
]}

机构：

[1] Univ Toronto, Dept ECE, Toronto, ON, Canada

[2] Nortel Networks, Ottawa, ON, Canada

来源：

2008 IEEE CSIC SYMPOSIUM | 2008年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the fastest full-rate retiming circuit reported to date in any semiconductor technology. By combining low- and high-V-T MOSFETs on the data and clock path, respectively, and CMOS-inverter based transimpedance amplifiers as low-noise, broadband preamplifiers, record speed is achieved with 1.2V supply. The power consumption of the 81GRz latch is only 9.6mW. On-wafer measurements demonstrate correct full-rate retiming up to 81Gb/s with jitter reduction and rise/fall time improvements.

引用

页码：182 / +

页数：2

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