Design Optimization and Modeling of Charge Trap Transistors (CTTs) in 14 nm FinFET Technologies

被引：12

作者：

Khan, Faraz ^{[1
,2
]}

Han, Min Soo ^{[2
]}

Moy, Dan ^{[1
]}

Katz, Robert ^{[1
]}

Jiang, Liu ^{[1
]}

Banghart, Edmund ^{[1
]}

Robson, Norman ^{[1
]}

Kirihata, Toshiaki ^{[1
]}

Woo, Jason C. S. ^{[2
]}

Iyer, Subramanian S. ^{[2
]}

机构：

[1] GlobalFoundries, Adv Technol Dev, East Fishkill, NY 12533 USA

[2] Univ Calif Los Angeles, Elect & Comp Engn Dept, Los Angeles, CA 90095 USA

来源：

IEEE ELECTRON DEVICE LETTERS | 2019年 / 40卷 / 07期

关键词：

Charge Trap Transistor (CTT); embedded non-volatile memory (eNVM); process-free; mask-free; high-k/metal gate (HKMG); CMOS;

D O I：

10.1109/LED.2019.2919871

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The Charge Trap Transistor (CTT) technology is an emerging memory solution that turns as-fabricated high-k/metal gate (HKMG) logic transistors into secure, embedded non-volatile memory (eNVM) elements with excellent data retention and operation capability at military grade temperatures. In other words, the CTTs offer a completely process-free and mask-free eNVM solution for advanced HKMG CMOS technology nodes. In this letter, bitcell design to enhance programming efficiency and modeling of the charge trapping behavior of CTTs in 14 nm FinFET technology is discussed.

引用

页码：1100 / 1103

页数：4

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