Expression equivalence checking using interval analysis

被引:6
作者
Ghodrat, Mohammad Ali [1 ]
Givargis, Tony
Nicolau, Alex
机构
[1] Univ Calif Irvine, Dept Comp Sci, Irvine, CA 92697 USA
[2] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
基金
美国国家科学基金会;
关键词
expression equivalence; interval analysis; mutual exclusion;
D O I
10.1109/TVLSI.2006.878471
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Arithmetic expressions are the fundamental building blocks of hardware and software systems. An important problem in computational theory is to decide if two arithmetic expressions are equivalent. However, the general problem of equivalence checking, in digital computers, belongs to the NP Hard class of problems. Moreover, existing general techniques for solving this decision problem are applicable to very simple expressions and impractical when applied to more complex expressions found in programs written in high-level languages. In this paper, we propose a method for solving the arithmetic expression equivalence problem using partial evaluation. In particular, our technique is specifically designed to solve the problem of equivalence checking of arithmetic expressions obtained from high-level language descriptions of hardware/software systems. In our method, we use interval analysis to substantially prune the domain space of arithmetic expressions and limit the evaluation effort to a sufficiently limited set of subspaces. Our results show that the proposed method is fast enough to be of use in practice.
引用
收藏
页码:830 / 842
页数:13
相关论文
共 25 条
[1]  
Aho A., 1988, Compilers - Principles, Techniques and Tools
[2]  
AKERS SB, 1978, IEEE T COMPUT, V27, P509, DOI 10.1109/TC.1978.1675141
[3]  
[Anonymous], 1994, SYNTHESIS OPTIMIZATI, DOI DOI 10.5555/541643
[4]   RTL-datapath verification using integer linear programming [J].
Brinkmann, R ;
Drechsler, R .
ASP-DAC/VLSI DESIGN 2002: 7TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE AND 15TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2002, :741-746
[5]   PATH-BASED SCHEDULING FOR SYNTHESIS [J].
CAMPOSANO, R .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1991, 10 (01) :85-93
[6]  
CHAIYAKUL V, 1993, P DES AUT C JUN, P413
[7]   MINCE: Matching INstructions using combinational equivalence for extensible processor [J].
Cheung, N ;
Parameswaran, S ;
Henkel, J ;
Chan, J .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, :1020-1025
[8]   Taylor Expansion Diagrams: A compact, canonical representation with applications to symbolic verification [J].
Ciesielski, MJ ;
Kalla, P ;
Zeng, ZH ;
Rouzeyre, B .
DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, 2002 PROCEEDINGS, 2002, :285-289
[9]  
CLARKE EM, 1993, ACM IEEE D, P54
[10]  
Dershowitz N., 1990, HDB THEORETICAL COMP