Multiplier-free bandpass channelizer for undersampled applications

被引：1
|
作者：
Santraine, A [1 ]
Leprince, S [1 ]
Taylor, F [1 ]
机构：
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
来源：
IEEE SIGNAL PROCESSING LETTERS | 2004年 / 11卷 / 11期
关键词：
channelizer; embedded processor; number theory; undersamping;
D O I：
10.1109/LSP.2004.835478
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Today, there is a strong motivation to increase the digital content of low-power wireless transceivers. Direct data conversion is often not possible, or practical, at high radio frequencies. In such instances, undersampling analog-to-digital converters (ADCs) are often used to alias information, residing above the ADC's Nyquist frequency, down to baseband as a set of nonoverlapping subbands. In this paper a low-complexity, programmable, band-selectable channelizer (a.k.a., digital downconverter) is presented that can efficiently access specific subbands; from an undersampled signal space.
引用
收藏
页码：904 / 907
页数：4
相关论文
共 50 条
  • [41] Dynamical analysis of an improved FitzHugh-Nagumo neuron model with multiplier-free implementation
    Xu, Quan
    Chen, Xiongjian
    Chen, Bei
    Wu, Huagan
    Li, Ze
    Bao, Han
    NONLINEAR DYNAMICS, 2023, 111 (09) : 8737 - 8749
  • [42] Dynamical analysis of an improved FitzHugh-Nagumo neuron model with multiplier-free implementation
    Quan Xu
    Xiongjian Chen
    Bei Chen
    Huagan Wu
    Ze Li
    Han Bao
    Nonlinear Dynamics, 2023, 111 : 8737 - 8749
  • [43] Fir filters with punctured radix-8 symmetric coefficients: Design and multiplier-free
    Boonyanant, P
    Tantaratana, S
    CIRCUITS SYSTEMS AND SIGNAL PROCESSING, 2002, 21 (04) : 345 - 367
  • [44] A Multiplier-Free Discrete Cosine Transform Architecture Using Approximate Full Adder and Subtractor
    Esmaeili, Elham
    Shiri, Nabiollah
    Rafiee, Mahmood
    Sadeghi, Ayoub
    IEEE EMBEDDED SYSTEMS LETTERS, 2024, 16 (04) : 441 - 444
  • [45] Computationally efficient direct multiplier-free minimum-phase FIR filter design
    Jovanovic-Dolecek, Gordana
    Fernandez-Vazquez, A.
    Alvarez, M. M.
    PROCEEDINGS OF THE 6TH INTERNATIONAL CARIBBEAN CONFERENCE ON DEVICES, CIRCUITS, AND SYSTEMS, 2006, : 43 - +
  • [46] A multiplier-free fixed-task digital CNN array for video segmentation system
    Paasio, A
    Paakkulainen, J
    Isoaho, J
    ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL III: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 710 - 713
  • [47] Time-area efficient multiplier-free recursive filter architectures for FPGA implementation
    Shajaan, M
    Sorensen, JA
    1996 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, CONFERENCE PROCEEDINGS, VOLS 1-6, 1996, : 3268 - 3271
  • [48] Multiplier-Free Phase Recovery With Polar-domain Multisymbol-Delay-Detector
    Tolmachev, Alex
    Tselniker, Igor
    Meltsin, Maxim
    Sigron, Itzik
    Dahan, David
    Shalom, Aviv
    Nazarathy, Moshe
    JOURNAL OF LIGHTWAVE TECHNOLOGY, 2013, 31 (23) : 3638 - 3650
  • [49] Nonseparable 2D lossless transforms based on multiplier-free lossless WHT
    Komatsu, K
    Sezaki, K
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2003, E86A (02): : 497 - 503
  • [50] Cascaded multiplier-free implementation of adaptive anti-jamming filter based on GNSS receiver
    Song, Jie
    Chen, Lei
    Lu, Zukun
    Li, Baiyu
    Liu, Zhe
    Xue, Zhihao
    Sun, Guangfu
    Liu, Wenhong
    FRONTIERS IN PHYSICS, 2024, 12
12345