Toward attojoule switching energy in logic transistors

被引:51
作者
Datta, Suman [1 ,2 ]
Chakraborty, Wriddhi [2 ]
Radosavljevic, Marko [3 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
[2] Univ Notre Dame, Dept Elect Engn, Notre Dame, IN 46556 USA
[3] Intel Corp, Log Technol Dev, Components Res, Hillsboro, OR USA
关键词
GATE STACK; TECHNOLOGY;
D O I
10.1126/science.ade7656
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling-the decrease of component sizes-with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.
引用
收藏
页码:733 / 740
页数:8
相关论文
共 37 条
[1]  
Adusumilli P, 2016, S VLSI TECH
[2]   Power and efficiency analysis of a realistic resonant tunneling diode thermoelectric [J].
Agarwal, Akshay ;
Muralidharan, Bhaskaran .
APPLIED PHYSICS LETTERS, 2014, 105 (01)
[3]  
[Anonymous], 2018, IEDM, DOI [10.1109/IEDM.2018.8614629, DOI 10.1109/IEDM.2018.8614629]
[4]  
[Anonymous], 2012, DIGEST TECHNICAL PAP
[5]   Contact module progress and challenges in advanced CMOS technologies [J].
Breil, Nicolas .
IITC2021: 2021 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE (IITC), 2021,
[6]   Pseudo-Static 1T Capacitorless DRAM using 22nm FDSOI for Cryogenic Cache Memory [J].
Chakraborty, Wriddhi ;
Saligram, Rakshith ;
Gupta, Aniket ;
San Jose, Matthew ;
Aabrar, Khandker Akif ;
Dutta, Sourav ;
Khanna, Abhishek ;
Raychowdhury, Arijit ;
Datta, Suman .
2021 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2021,
[7]  
Chakraborty W., 2022, DIGEST TECHNICAL PAP, P302
[8]  
Chakraborty W., 2021, DIGEST TECHNICAL PAP, P1
[9]  
Chakraborty W., 2019, IEEE INT EL DEV M IE
[10]   High-κ/metal-gate stack and its MOSFET characteristics [J].
Chau, R ;
Datta, S ;
Doczy, M ;
Doyle, B ;
Kavalieros, J ;
Metz, M .
IEEE ELECTRON DEVICE LETTERS, 2004, 25 (06) :408-410