Performance Enhancement in N2 Plasma Modified AlGaN/AlN/GaN MOS-HEMT Using HfAlOX Gate Dielectric with Γ-Shaped Gate Engineering

被引:11
作者
Yang, Shun-Kai [1 ]
Mazumder, Soumen [1 ]
Wu, Zhan-Gao [1 ]
Wang, Yeong-Her [1 ]
机构
[1] Natl Cheng Kung Univ, Inst Microelect, Dept Elect Engn, Tainan 701, Taiwan
关键词
AlGaN/AlN/GaN; MOS-HEMT; HfAlOX; HfO2; interface trap density; post-deposition annealing (PDA); Gamma-shaped gate; flicker noise;
D O I
10.3390/ma14061534
中图分类号
O64 [物理化学(理论化学)、化学物理学];
学科分类号
070304 ; 081704 ;
摘要
In this paper, we have demonstrated the optimized device performance in the Gamma-shaped gate AlGaN/AlN/GaN metal oxide semiconductor high electron mobility transistor (MOS-HEMT) by incorporating aluminum into atomic layer deposited (ALD) HfO2 and comparing it with the commonly used HfO2 gate dielectric with the N-2 surface plasma treatment. The inclusion of Al in the HfO2 increased the crystalline temperature (similar to 1000 degrees C) of hafnium aluminate (HfAlOX) and kept the material in the amorphous stage even at very high annealing temperature (>800 degrees C), which subsequently improved the device performance. The gate leakage current (I-G) was significantly reduced with the increasing post deposition annealing (PDA) temperature from 300 to 600 degrees C in HfAlOX-based MOS-HEMT, compared to the HfO2-based device. In comparison with HfO2 gate dielectric, the interface state density (D-it) can be reduced significantly using HfAlOX due to the effective passivation of the dangling bond. The greater band offset of the HfAlOX than HfO2 reduces the tunneling current through the gate dielectric at room temperature (RT), which resulted in the lower I-G in Gamma-gate HfAlOX MOS-HEMT. Moreover, I-G was reduced more than one order of magnitude in HfAlOX MOS-HEMT by the N-2 surface plasma treatment, due to reduction of N-2 vacancies which were created by ICP dry etching. The N-2 plasma treated Gamma-shaped gate HfAlOX-based MOS-HEMT exhibited a decent performance with I-DMAX of 870 mA/mm, G(MMAX) of 118 mS/mm, threshold voltage (V-TH) of -3.55 V, higher I-ON/I-OFF ratio of approximately 1.8 x 10(9), subthreshold slope (SS) of 90 mV/dec, and a high V-BR of 195 V with reduced gate leakage current of 1.3 x 10(-10) A/mm.
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页数:12
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