Performance Analysis of ESD Structures in 130 nm CMOS Technology for Low-Power Applications

被引：1

作者：

Nagy, Lukas ^{[1
]}

Chvala, Ales ^{[1
]}

Marek, Juraj ^{[1
]}

Potocny, Miroslav ^{[1
]}

Stopjakova, Viera ^{[1
]}

机构：

[1] Slovak Univ Technol Bratislava, Fac Elect Engn & Informat Technol, Inst Elect & Photon, Bratislava, Slovakia

来源：

2019 29TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA) | 2019年

关键词：

Low-Power; Low-Voltage; ESD structure; TCAD simulation; VerilogA model; DESIGN;

D O I：

10.1109/radioelek.2019.8733421

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper addresses static as well as dynamic performance analysis of a standard ESD structure fabricated in 130 nm CMOS technology. The original design of the ESD structures was aimed at power supply voltage of 1.2 V and usage of grounded-gate NMOS and PMOS devices. We investigated the properties of the presented ESD structure using a lowered value of the supply voltage, since the target application will be within a low-voltage / low-power systems with V-DD = 0.6 V and V-DD = 0.4 V. The comparison of the measured and simulated data is carried out and discussed. The paper also deals with the development of a novel high-accuracy VerilogA model in order to use more realistic load created by real ESD structures.

引用

页码：28 / 33

页数：6

共 8 条

[1] [Anonymous], 2017, 2017 IEEE SENS APPL
[2] Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process
Chiu, Po-Yen
Ker, Ming-Dou
Tsai, Fu-Yi
Chang, Yeong-Jar
[J]. 2009 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, VOLS 1 AND 2, 2009, : 750 - +
[3] Fan XJ, 2017, 2017 2ND IEEE INTERNATIONAL CONFERENCE ON CLOUD COMPUTING AND BIG DATA ANALYSIS (ICCCBDA 2017), P1, DOI 10.1109/ICCCBDA.2017.7951874
[4] Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
Ker, MD
Hsu, KC
[J]. IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2005, 5 (02) : 235 - 249
[5] Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
Ker, Ming-Dou
Wang, Chang-Tzu
Tang, Tien-Hao
Su, Kuan-Cbeng
[J]. 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL, 2007, : 594 - +
[6] Linten D, 2013, INT RELIAB PHY SYM
[7] Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology
Nagy, L.
Arbet, D.
Kovac, M.
Potocny, M.
Stopjakova, V
[J]. 2018 IEEE 21ST INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS (DDECS), 2018, : 51 - 54
[8] Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples
Stopjakova, Viera
Rakus, Matej
Kovac, Martin
Arbet, Daniel
Nagy, Lukas
Sovcik, Michal
Potocny, Miroslav
[J]. RADIOENGINEERING, 2018, 27 (01) : 171 - 185

← 1 →