Performance Analysis of ESD Structures in 130 nm CMOS Technology for Low-Power Applications

被引：1

作者：

Nagy, Lukas ^{[1
]}

Chvala, Ales ^{[1
]}

Marek, Juraj ^{[1
]}

Potocny, Miroslav ^{[1
]}

Stopjakova, Viera ^{[1
]}

机构：

[1] Slovak Univ Technol Bratislava, Fac Elect Engn & Informat Technol, Inst Elect & Photon, Bratislava, Slovakia

来源：

2019 29TH INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA) | 2019年

关键词：

Low-Power; Low-Voltage; ESD structure; TCAD simulation; VerilogA model; DESIGN;

D O I：

10.1109/radioelek.2019.8733421

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper addresses static as well as dynamic performance analysis of a standard ESD structure fabricated in 130 nm CMOS technology. The original design of the ESD structures was aimed at power supply voltage of 1.2 V and usage of grounded-gate NMOS and PMOS devices. We investigated the properties of the presented ESD structure using a lowered value of the supply voltage, since the target application will be within a low-voltage / low-power systems with V-DD = 0.6 V and V-DD = 0.4 V. The comparison of the measured and simulated data is carried out and discussed. The paper also deals with the development of a novel high-accuracy VerilogA model in order to use more realistic load created by real ESD structures.

引用

页码：28 / 33

页数：6

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