共 18 条
[1]
Akers S. B., 1987, International Test Conference 1987 Proceedings: Integration of Test with Design and Manufacturing (Cat. No.87CH2347-2), P1100
[2]
[Anonymous], 2007, PROC INT TEST CONF
[3]
Properties of the input pattern fault model
[J].
INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS,
1997,
:372-380
[4]
Cho K., 2005, P IEEE INT C TEST, P1, DOI DOI 10.1109/TEST.2005.1584040
[5]
Evaluation of test metrics: Stuck-at, bridge coverage estimate and gate exhaustive
[J].
24TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS,
2006,
:66-71
[6]
Test set compaction algorithms for combinational circuits
[J].
1998 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN: DIGEST OF TECHNICAL PAPERS,
1998,
:283-289
[8]
Huang Y.-H., 2017, PROC VLSI TEST S, P1
[9]
The region-exhaustive fault model
[J].
PROCEEDINGS OF THE 16TH ASIAN TEST SYMPOSIUM,
2007,
:13-18
[10]
Jau-Shien Chang, 1992, Proceedings. First Asian Test Symposium (ATS '92) (Cat. No.TH0458-0), P20, DOI 10.1109/ATS.1992.224429