A 40-GHz flip-hop-based frequency divider

被引：18

作者：

Heydari, Payam ^{[1
]}

Mohanavelu, Ravindran

机构：

[1] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA

[2] Intel Corp, Folsom, CA 95630 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 12期

关键词：

current-mode logic (CML); frequency divider (FD); high speed; latch; wireline transceiver;

D O I：

10.1109/TCSII.2006.885393

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mu m SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage.

引用

页码：1358 / 1362

页数：5

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