Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

被引：0

作者：

Sarkhel, Saheli ^{[1
]}

Saha, Priyanka ^{[2
]}

Sarkar, Subir Kumar ^{[2
]}

机构：

[1] Netaji Subhash Engn Coll, Dept Elect & Commun Engn, Kolkata 700152, India

[2] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India

来源：

SILICON | 2019年 / 11卷 / 03期

关键词：

MOSFET; Graded channel; Triple material gate; Short channel effects; High-k gate stack; Analytical modeling;

D O I：

10.1007/s12633-018-9950-9

中图分类号：

O64 [物理化学（理论化学）、化学物理学];

学科分类号：

070304 ; 081704 ;

摘要：

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

引用

页码：1421 / 1428

页数：8

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