Configurable Links for 3D Network On-Chip based on Mapping Algorithm

Network-on-chip (NoC) emerged as a promising alternative to the bus and point-to-point communication architectures. Recently 3D NoC become a hot topic. While complex 3D NoCs will generate a large amount of data to deal with, NoCs suffer from intermittent congestions and link overflows, especially when the network bandwidth is limited by the area and energy budget. In this paper, we explore a technique for balance link bandwidth based mapping algorithm dedicated to NoC. After mapping we double the link bandwidth according to the high-bandwidth allocation through the network busy nodes, while the remaining links bandwidth assignment unchanged. Experiments results show that the network average delay is reduced by 25% through doubling the central loop bandwidth.