The Design and Implementation of High-Speed Codec Based on FPGA

被引：0

作者：

Ren, Weiji ^{[1
]}

Liu, Hao ^{[1
]}

机构：

[1] Beijing Inst Technol, Sch Informat & Elect, Beijing, Peoples R China

来源：

2018 10TH INTERNATIONAL CONFERENCE ON COMMUNICATION SOFTWARE AND NETWORKS (ICCSN) | 2018年

关键词：

LDPC code; quasi-cyclic LDPC code; high throughput;

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

This article mainly proposes a high-speed encoding and decoding method for LDPC code on FPGA. This method converts a quasi-cyclic LDPC code into a block quasi-cyclic LDPC code, and uses a similar transformation to generate a corresponding generator matrix, thereby improving the parallelism of encoder and decoder and making them have high throughput. Finally, we implemented high-speed encoding and decoding on the FPGA chip of the Kintex7 system by using the CCSDS-recommended (8176, 7154) LDPC code, and these encoder and decoder achieve a throughput of 2.97 Gbps under the condition of 5 iterations.

引用

页码：427 / 432

页数：6

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