A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS

被引:149
作者
Wu, Wanghua [1 ]
Staszewski, Robert Bogdan [1 ]
Long, John R. [1 ]
机构
[1] Delft Univ Technol, Elect Res Lab DIMES, NL-2628 CD Delft, Netherlands
基金
欧洲研究理事会;
关键词
60; GHz; all-digital phase-locked loop (ADPLL); CMOS technology; digital calibration; FMCW radar; mm-wave frequency synthesizer; multi-rate two-point frequency modulation; PHASE-LOCKED LOOP; CONVERTER; TIME; OSCILLATOR; COARSE; TDC;
D O I
10.1109/JSSC.2014.2301764
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A mm-wave digital transmitter based on a 60 GHz all-digital phase-locked loop (ADPLL) with wideband frequency modulation (FM) for FMCW radar applications is proposed. The fractional-N ADPLL employs a high-resolution 60 GHz digitally-controlled oscillator (DCO) and is capable of multi-rate two-point FM. It achieves a measured rms jitter of 590.2 fs, while the loop settles within 3 mu s. The measured reference spur is only -74 dBc, the fractional spurs are below -62 dBc, with no other significant spurs. A closed-loop DCO gain linearization scheme realizes a GHz-level triangular chirp across multiple DCO tuning banks with a measured frequency error (i.e., nonlinearity) in the FMCW ramp of only 117 kHz(rms) for a 62 GHz carrier with 1.22 GHz bandwidth. The synthesizer is transformer-coupled to a 3-stage neutralized power amplifier (PA) that delivers +5 dBm to a 50 Omega load. Implemented in 65 nm CMOS, the transmitter prototype (including PA) consumes 89 mW from a 1.2 V supply.
引用
收藏
页码:1081 / 1096
页数:16
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